Extending battery life by reducing power consumption in mobile devices is a challenging task as the processing power for their integrated circuits such as a system-on-a-chip (SOC) continues to increase. To provide reduced power consumption in the dynamic random access memory (DRAM) devices for the mobile market, various low power double data rate (LPDDR) DRAM standards have evolved in which the DRAM may vary the signaling voltage used to transmit data to the receiving SOC. In a low voltage mode, the DRAM uses a lower signaling voltage such as 0.5 V whereas in a high voltage mode the DRAM may use a higher signaling voltage such as 0.9V or 1.1V. In contrast, the receiver power supply voltage (VDDIO) used by the receiver in the SOC to receive the data from the external DRAM is independent of the DRAM signaling voltage but VDDIO may also vary widely such as from 0.5 to 1.1V depending upon the mode of operation within the SOC.
The independent variation between the DRAM signaling voltage and power supply voltage VDDIO in the receiver makes low power operation challenging. For example, it is convenient to receive the data from the DRAM by driving the gates of a serially-stacked PMOS and NMOS transistor pair in an inverter with the received data signal. If the power supply voltage VDDIO is relatively high (e.g., 1.1V) whereas the DRAM signaling voltage is relatively low, the PMOS transistor in the receiver's inverter will still be weakly on despite receiving a binary high signal because the received 0.5 volt signal acts as a weak zero to the PMOS since its source is tied to the 1.1 volt power supply voltage. The inverter will thus undesirably conduct current since the PMOS transistor is not fully off. Moreover, it is a challenge to construct a receiver that is tolerant to the higher voltage ranges for the input signal yet regains enough input amplification to work with the lower input voltage swings.
Accordingly, there is a need in the art for improved low power receivers with wide input voltage ranges.